1. Field of the Invention
The present invention relates to techniques for communicating signals between semiconductor dies. More specifically, the present invention relates to a method and an apparatus for communication between semiconductor dies by routing electrical signals based on alignment between the semiconductor dies.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems, including tens of millions of transistors, into a single semiconductor chip. Integrating such large-scale systems onto a single semiconductor chip increases the speed at which such systems can operate, because signals between system components do not have to cross chip boundaries, and are not subject to lengthy chip-to-chip propagation delays. Moreover, integrating large-scale systems onto a single semiconductor chip significantly reduces production costs, because fewer semiconductor chips are required to perform a given computational task.
Unfortunately, these advances in semiconductor technology have not been matched by corresponding advances in inter-chip communication technology. Semiconductor chips are typically integrated onto a printed circuit board that contains multiple layers of signal lines for inter-chip communication. However, signal lines on a semiconductor chip are about 100 times more densely packed than signal lines on a printed circuit board. Consequently, only a tiny fraction of the signal lines on a semiconductor chip can be routed across the printed circuit board to other chips. This problem is beginning to create a bottleneck that continues to grow as semiconductor integration densities continue to increase.
Researchers have begun to investigate alternative techniques for communicating between semiconductor chips. One promising technique involves integrating arrays of capacitive transmitters and receivers onto semiconductor chips to facilitate inter-chip communication. If a first chip is situated face-to-face with a second chip so that transmitter pads on the first chip are capacitively coupled with receiver pads on the second chip, it becomes possible to transmit signals directly from the first chip to the second chip without having to route the signal through intervening signal lines within a printed circuit board.
However, it is not a simple matter to align the chips properly. It is possible to align the chips by assigning a charge to conducting plates on one chip, and detecting a specific pattern of charges that are induced in plates on a facing chip. An existing system improves upon this technique by providing a plurality of conductive elements on the first chip and a plurality of conductive elements on the second chip with a different spacing than the conductive elements on the first chip. When the conductive elements on the first chip overlap the conductive elements on the second chip a vernier is created, thereby allowing the alignment between the chips to be determined, thereby allowing the chips to be positioned so as to minimize misalignment problems.
This existing system, however, has limitations. Even with very careful mechanical assembly, the chips still have some residual misalignment. Misalignment can possibly cause each receiving pad to span two transmitting pads, thereby destroying a received signal. In theory, satisfactory communication requires alignment such that the residual misalignment is less than half of a pitch between the pads. In practice, the alignment requirements may be more stringent. Furthermore, thermal expansion and the effects of mechanical vibration may make it difficult to achieve and maintain such accurate alignment.
What is needed is a method and an apparatus to facilitate capacitive inter-chip communications without the problems listed above.